1. Field of the Invention
The invention relates generally to apparatus for controlling the storage of data in a data processor and more particularly, to apparatus for detecting and reporting errors in data stored in a data processor.
2. Description of the Related Art
A typical data processor includes a central processing unit (CPU) which executes instructions which either process data or cause the transfer of data among different functional units of the data processor. A main storage unit having a relatively large storage capacity ordinarily stores programs and data used by the programs. Data to be processed by the central processing unit ordinarily is transferred from the main storage unit to a cache memory before processing actually begins. The cache memory interfaces directly with the central processing unit. Usually, the cache has a relatively low storage capacity but operates at relatively high speed to provide the data to the central processing unit for use during execution of a corresponding program.
Frequently, a variety of processes share the use of the CPU. Moreover, often the CPU interrupts the execution of a program corresponding to a first active process in order to execute a program corresponding to a second process which takes precedence over the first active process. In order to execute the program corresponding to the second process, however, it ordinarily is necessary for the data corresponding to the second process to be moved into the cache. Consequently, often it is necessary to move out the data corresponding to the first process from the cache in order to make room for the data corresponding to the second process. Typically, the data corresponding to the first process is moved into the main storage unit for storage during execution by the CPU of the program corresponding to the second process.
Subsequently, after the CPU has executed the program corresponding to the second process, the data corresponding to the first process, once again can be moved into the cache. Moreover, a typical data processor ordinarily includes a data storage control system which controls the transfer of data between the cache and the main storage unit such that data associated with programs actively being executed by the central processing unit can be moved into the cache, and data associated with processes to be executed later by the CPU can be moved out of the cache and into the main storage unit.
One problem associated with the storage of data by a data processor in general, and associated with the transfer of data between the cache and the main storage unit in particular, stems from the occurrence of errors in the stored data. Errors are manifested, for example, as unwanted changes in the binary state of bits within a byte or line of data. Errors can occur in a variety of locations such as in the cache, in the main storage unit or in the course of transferring the data between the cache and the main storage unit. Since data errors detrimentally affect the performance of the data processor, the data storage control system ordinarily includes components directed to detecting and reporting such errors.
For example, in the past, error checking and correcting (ECC) codes frequently were used to detect errors occurring in data stored in the cache and to correct certain of the errors. More specifically, an ECC code was generated each time data was moved into the cache. The ECC code, for example, could comprise a set of single bit binary signals, each of which represented a parity bit covering a particular set of data bits, each respective data bit being covered by more than one ECC code bit. The ECC code was stored in conjunction with the corresponding data. Subsequently, when the data was moved out of the cache, the ECC code was used to detect the occurrence of errors in the data and to correct certain of those errors.
Since the cache and the main storage unit often were physically spaced apart within the data processor by a relatively significant distance, errors often could occur in the course of the transfer. Consequently, the data typically was covered by parity during the transfer in order to detect occurrences of errors in the course of the transfer.
For example, commonly assigned U.S. Pat. No. 4,625,773 issued Nov. 25, 1986 entitled, APPARATUS FOR FAST DATA STORAGE WITH DEFERRED ERROR REPORTING and commonly assigned continuation application Ser. No. 790,269 filed Oct. 22, 1985 now abandoned and entitled, APPARATUS FOR STORING DATA WITH DEFERRED UNCORRECTABLE ERROR REPORTING which is a continuation of commonly assigned application Ser. No. 527,671, filed Aug. 30, 1983 and now abandoned generally pertain to the reporting of errors present or occurring in the course of the move-out of data signals from a cache to a main storage unit. Moreover, the apparatus described in the aforementioned patent applications defer the reporting of errors until the data is to be moved back into the main storage unit. Unfortunately, the earlier apparatus often did not distinguish between errors occurring in the data signals in the course of the move-out of the data signals from the cache to the main storage unit and errors occurring in the course of the storage of the data signals in the main storage unit.
Thus, there has been a need for an apparatus for detecting and reporting errors present or occurring in data signals in the course of the move-out of the signals from a cache to a main storage unit and for distinguishing between those errors and errors occurring in the course of the storage of the data signals in the main storage unit. The present invention meets this need.